Архитектура процессоров x86 и многозадачность

Уровень 0 · материалов: 3

В кластер входят документы, посвященные низкоуровневой реализации многозадачности и устройству регистров процессоров семейства x86.

Общие признаки: архитектура x86, многозадачность, управление регистрами, Intel 80386

Группа выше: Процессоры Intel и архитектура x86

Материалы

• #10529 — Multitasking Mechanics on the 80386 Processor — Представитель этого кластера

  Как вы считаете, как работает многозадачность на 80386? — sidristij

  Смысл: The text is a metadata record for a technical discussion regarding the architectural implementation of multitasking on the Intel 80386 microprocessor.

  A metadata record for a community article discussing the technical workings of multitasking on the legacy Intel 80386 processor.

• #9484 — Implementing Cooperative Fibers with C++ and x86-64 Assembler

  Любителям x86-64 assembler посвящается: DIY волокна в C++ — cvigi

  Смысл: The main idea is to demonstrate how to build a cooperative multitasking mechanism (fibers) from scratch by manually managing CPU registers and memory stacks using a combination of C++ and x86/x64 Assembler, highlighting the architectural differences between 32-bit and 64-bit execution environments.

  A deep-dive technical tutorial on creating a custom cooperative fiber system using C++ and x86/x64 assembly to manually manage context switching and stacks.

• #29126 — The Complex Register Architecture of Intel 80386

  Абсурдно усложнённая схема регистров в Intel 80386 — Bright_Translate

  Смысл: The main idea is that the Intel 80386's physical register layout is absurdly complex because it had to balance high performance with strict backward compatibility for 8-bit and 16-bit operations, leading to a fragmented design with six different circuit types.

  An in-depth reverse-engineering analysis of the Intel 80386 silicon reveals a highly fragmented register system designed to support legacy x86 compatibility.